NDLI: An efficient method to screen resistive opens under presence of process variation

Content Provider	IEEE Xplore Digital Library
Author	Seongmoon Wang
Copyright Year	2011
Description	Author affiliation: Samsung Austin Semiconductor, SARC, TX 78754, USA (Seongmoon Wang)
Abstract	In this paper, a cost efficient test methodology to screen chips that have resistive open defects under the presence of process variation is proposed. The proposed test methodology is based on small delay defect testing. The entire test session is divided into several subsessions. In each subsession, test patterns are applied with a different frequency of test clock, all of which are faster than the rated clock. Unlike others, different test patterns are generated and applied in each subsession to reduce test application time. A simple three step screening method is also proposed. The first step identifies scan outputs that can fail only if there are defects under the possible worst case process variation. In the second step, we assume that a chip failed due to a defect if the number of faulty scan outputs in a test pattern is much larger than that of faulty scan outputs of a typical defect free chip. Finally, the third step screens defective chips by comparing the number of fail patterns. Among 10 benchmark circuits used for the experiments, the proposed method was able to screen successfully more than 90 % of defective chips for 8 circuits.
Starting Page	122
Ending Page	127
File Size	671346
Page Count	6
File Format	PDF
ISBN	9781612846576
ISSN	10930167
e-ISBN	9781612846569
DOI	10.1109/VTS.2011.5783771
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Clocks Circuit faults Logic gates Wires Silicon Automatic test pattern generation
Content Type	Text
Resource Type	Article

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