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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Rajendran, J. Jyothi, V. Sinanoglu, O. Karri, R. |
| Copyright Year | 2011 |
| Description | Author affiliation: Computer Eng. Department, New York University, Abu Dhabi, USA (Sinanoglu, O.) || ECE Department, Polytechnic Institute of New York University, USA (Rajendran, J.; Jyothi, V.; Karri, R.) |
| Abstract | Due to the increasing opportunities for malicious inclusions in hardware, Design-for-Trust (DFTr) is emerging as an important IC design methodology. In order to incorporate the DFTr techniques into the IC development cycle, they have to be practical in terms of their Trojan detection capabilities, hardware overhead, and test cost. We propose a non-invasive DFTr technique, which can detect Trojans in the presence of process variations and measurement errors. This technique can detect Trojans that are inserted in all or a subset of the ICs. It is applicable to both ASICs and FPGA implementations. Circuit paths in a design are reconfigured into ring $oscillators^{1}$ (ROs) by adding a small amount of logic. Trojans are detected by observing the changes in the frequency of the ROs. An algorithm is provided to secure all the gates, while reducing the hardware overhead. We analyzed the coverage, area and test time overhead of the proposed DFTr technique. To demonstrate its effectiveness in the real world, the proposed technique had been validated by a red-team blue-team approach. |
| Starting Page | 105 |
| Ending Page | 110 |
| File Size | 2038635 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781612846576 |
| ISSN | 10930167 |
| e-ISBN | 9781612846569 |
| DOI | 10.1109/VTS.2011.5783766 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-05-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Trojan horses Integrated circuits Semiconductor device measurement Hardware Delay Fabrication Power measurement |
| Content Type | Text |
| Resource Type | Article |
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