NDLI: Programmable extended SEC-DED codes for memory errors

Content Provider	IEEE Xplore Digital Library
Author	Gherman, V. Evain, S. Auzanneau, F. Bonhomme, Y.
Copyright Year	2011
Description	Author affiliation: CEA, LIST, Embedded Systems Reliability Laboratory, Point Courrier 94, 91191 Gif-sur-Yvette CEDEX, FRANCE (Gherman, V.; Evain, S.; Auzanneau, F.; Bonhomme, Y.)
Abstract	Redundant memory columns are an essential ingredient of memory design for yield and reliability. They are used either as spare columns for the replacement of completely defective regular columns or to store check-bits for error detection and correction codes. Column replacement allows to mask isolated malfunctioning storage cells as well. Unfortunately, the number of columns with defective storage cells that can be masked in this way cannot exceed the number of spare columns which is usually quite low. Here, we propose a way to increase the capacity of masking memory columns with isolated defective storage cells using spare memory columns. For this purpose, single error correction and double error detection (SEC-DED) codes already available for the protection against soft errors are extended such that all double-bit errors which affect a fixed sub-set of bit positions in the code words can be corrected. The cardinality of this sub-set is significantly higher than the number of spare columns. A bit-swapper is employed to map the bit positions that are protected by the extended SEC-DED code against double-bit errors to the memory columns with defective storage cells. In this way, single-bit soft-errors affecting any bit position can be corrected simultaneously with single-bit hard errors induced by any sub-set of memory columns. The bit-swapper can be dynamically reconfigured based on status information that designates the memory columns with defective storage cells. This facilitates the integration into built-in self-repair (BISR) schemes.
Starting Page	140
Ending Page	145
File Size	768774
Page Count	6
File Format	PDF
ISBN	9781612846576
ISSN	10930167
e-ISBN	9781612846569
DOI	10.1109/VTS.2011.5783774
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Maintenance engineering Systematics Indexes Manganese Multiplexing Block codes Memory management error correction yield memory repair BISR
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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