NDLI: A pipelined fuzzy reasoning processor and its software development system

Content Provider	IEEE Xplore Digital Library
Author	Hwai-Tsu Chang Chen, O.T.-C. Wei-Juin Chen Shyh-Rong Luo Yao-Chou Lu Jyuo-Min Shyu
Copyright Year	1995
Description	Author affiliation: Comput. & Commun. Res. Lab., Ind. Technol. Res. Inst., Hsinchu, Taiwan (Hwai-Tsu Chang; Chen, O.T.-C.; Wei-Juin Chen; Shyh-Rong Luo; Yao-Chou Lu; Jyuo-Min Shyu)
Abstract	Fuzzy reasoning processors have been employed in many commercial and industrial applications. A high-performance pipelined, single-instruction-stream, and single-data-stream architecture of a fuzzy reasoning engine has been designed. Based on this architecture, the proposed VLSI processor for embedded real-time fuzzy logic applications was fabricated in a 0.8-/spl mu/m CMOS technology. Its computation power can reach 2.5 Million Fuzzy Logic Inferences Per Second (MFLIPS) at a system clock of 20 MHz. In order to efficiently realize fuzzy applications, a software development system under Microsoft Windows has also been designed.
Starting Page	252
Ending Page	256
File Size	466202
Page Count	5
File Format	PDF
ISBN	078032773X
DOI	10.1109/VTSA.1995.524673
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-31
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fuzzy reasoning Programming Application software Computer architecture Fuzzy logic CMOS technology Engines Very large scale integration CMOS process Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A pipelined fuzzy reasoning processor with software development system and its application on the crane control problem

A VLSI fuzzy processor with parallel rule execution

A pipelined VLSI arithmetic architecture

VLSI design and realisation of a 4 input high speed fuzzy processor

Industrial Application of High Level Design Tools in Large Computer System Development

Design of a 50 MFIPS fuzzy controller ASIC

CMOS implementation of a 32 b computer

Design and architecture for a multi-mode pipelined, floating-point adder

VLSI-DLMs : A Structured Approach to Chip Architecture

A pipelined fuzzy reasoning processor and its software development system

Similar Documents

A pipelined fuzzy reasoning processor with software development system and its application on the crane control problem

A VLSI fuzzy processor with parallel rule execution

A pipelined VLSI arithmetic architecture

VLSI design and realisation of a 4 input high speed fuzzy processor

Industrial Application of High Level Design Tools in Large Computer System Development

Design of a 50 MFIPS fuzzy controller ASIC

CMOS implementation of a 32 b computer

Design and architecture for a multi-mode pipelined, floating-point adder

VLSI-DLMs : A Structured Approach to Chip Architecture

A pipelined fuzzy reasoning processor and its software development system