NDLI: Finite state machine partitioning for I/O-limited design

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Finite state machine partitioning for I/O-limited design

Content Provider	IEEE Xplore Digital Library
Author	Ming-Ter Kuo Lung-Tien Liu Chung-Kuan Cheng
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA (Ming-Ter Kuo; Lung-Tien Liu; Chung-Kuan Cheng)
Abstract	We proposed a Finite State Machine (FSM) partitioning procedure for minimizing the number of inputs/outputs of FSMs. The FSM partition is obtained by partitioning the set of transitions that describe the behavior of an FSM. An extended FM-based graph partitioning algorithm is applied for transition partitioning. We also devise a state information minimization technique to further reduce the number of interconnections between the FSMs required for communication. Experimental results for MCNC benchmarks show that our algorithm has favorable results over circuit partitioning algorithms on the netlist level.
Starting Page	68
Ending Page	72
File Size	507336
Page Count	5
File Format	PDF
ISBN	078032773X
DOI	10.1109/VTSA.1995.524636
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-31
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automata Partitioning algorithms Minimization Circuit synthesis Logic devices Clocks Programmable logic devices Pins Circuit testing Benchmark testing
Content Type	Text
Resource Type	Article

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