NDLI: On-chip decoupling capacitor optimization for high-performance VLSI design

Content Provider	IEEE Xplore Digital Library
Author	Chen, H.H. Schuster, S.E.
Copyright Year	1995
Description	Author affiliation: Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Chen, H.H.; Schuster, S.E.)
Abstract	This paper describes the on-chip power bus modeling and switching noise analysis for high performance circuit design, and the methodology to optimize the placement of on-chip decoupling capacitors. The switching noise is analyzed at both the package level and the chip level. An equivalent circuit which consists of time-varying resistors, loading capacitors, and decoupling capacitors, is used to simulate the switching activities of functional blocks. Both the resistive and inductive voltage drops on the power bus are modelled to identify the hot spots on the chip and /spl Delta/V across the chip. Based on the noise analysis results, a decoupling capacitor insertion algorithm is proposed to determine the amount of decoupling capacitance needed to keep the power supply voltage within specification, and optimize the final size and location of on-chip decoupling capacitors.
Starting Page	99
Ending Page	103
File Size	581750
Page Count	5
File Format	PDF
ISBN	078032773X
DOI	10.1109/VTSA.1995.524641
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-31
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Circuit noise Switched capacitor circuits Switching circuits Voltage Performance analysis Circuit synthesis Design optimization Noise level Packaging
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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