NDLI: Design and architecture for a multi-mode pipelined, floating-point adder

Content Provider	IEEE Xplore Digital Library
Author	Gillam, K.R. Jones, K.R.
Copyright Year	1991
Description	Author affiliation: Space Syst. Div., Los Angeles AFB, CA, USA (Gillam, K.R.)
Abstract	The authors present the design and architecture of a VLSI floating-point adder (FPA). The multi-mode FPA is capable of both single-precision (32-b) and double-precision (64-b) arithmetic and was developed using CMOS technology. The adder is designed for a 40-MHz clock using a pipelined architecture with a two-cycle latency. Area is minimized as hardware is shared for both single-precision and double-precision operations. Two single-precision operations in parallel are possible providing 80-MFLOPS operation. Double-precision operations yield 40-MFLOPS. With the exception of denormalized number representation, the FPA is fully compliant with the IEEE Standard, for floating-point arithmetic. In addition to floating-point operations, the FPA is capable of performing 32-b integer operations. Five format conversions can be performed by the FPA on the four formats that are supported: single-precision, double-precision, integer and block floating-point.<>
Starting Page	73
Ending Page	76
File Size	281233
Page Count	4
File Format	PDF
ISBN	0780300858
DOI	10.1109/NAECON.1991.165725
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-05-20
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Latches Timing Clocks Adders Space technology Very large scale integration Arithmetic CMOS technology Pipelines Logic
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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