NDLI: Process and local layout effect interaction on a high performance planar 20nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Sato, F. Ramachandran, R. Van Meer, H. Cho, K.H. Ozbek, A. Yang, X. Liu, Y. Li, Z. Wu, X. Jain, S. Utomo, H. Kwon, U. Park, Y. Tan, W.L. Dai, X. Lai, W. Kim, J. Jones, D. Ganz, M. Bae, D.H. Lallement, R. Vemula, S.C. Kwon, T. Lee, P. Qi, Y. Weybright, M. Scholze, A. Bingert, R. King, J. Sherony, M. Eller, M. Shang, H. Tabakman, K. Narayanan, V. Samavedam, S. Divakaruni, R.
Copyright Year	2013
Description	Author affiliation: IBM Microelectron., Hopewell Junction, NY, USA (Sato, F.; Ramachandran, R.; Ozbek, A.; Li, Z.; Jain, S.; Utomo, H.; Kwon, U.; Lai, W.; Weybright, M.; Scholze, A.; King, J.; Sherony, M.; Shang, H.; Tabakman, K.; Narayanan, V.; Divakaruni, R.) \|\| GLOBALFOUNDRIES, Hopewell Junction, NY, USA (Van Meer, H.; Yang, X.; Liu, Y.; Wu, X.; Tan, W.L.; Dai, X.; Jones, D.; Ganz, M.; Vemula, S.C.; Kwon, T.; Lee, P.; Qi, Y.; Eller, M.; Samavedam, S.) \|\| Samsung Electron., Hopewell Junction, NY, USA (Cho, K.H.; Park, Y.; Kim, J.; Bae, D.H.) \|\| STMicroelectron., Hopewell Junction, NY, USA (Lallement, R.; Bingert, R.) As technology has advanced, layout dependent device parameter shifts are becoming more influential to the actual circuit operation and performance, such that design style differences could create systematic device variability due to layout unless those effect are minimized and well captured in the device model[1]. In this paper, we characterize the device layout effects on a high performance planar 20nm CMOS technology for low power mobile applications [2], and demonstrate a layout effect reduction by optimizing key process elements while improving device performance. Nfet/pfet boundary proximity in Replacement Metal Gate (RMG), Length of active area (LOD or SA/SB) and gate pitch dependency are discussed in terms of Stress Memorization Technique (SMT) and embedded SiGe (eSiGe) processes.
Sponsorship	IEEE Electron Devices Soc.
File Size	873537
File Format	PDF
ISBN	9781467352260
ISSN	21589682
e-ISBN	9784863483477
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-11
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP
Subject Keyword	Logic gates Performance evaluation Layout Metals Stress Proximity effects Stacking
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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