NDLI: Innovative through-Si 3D lithography for ultimate self-aligned planar Double-Gate and Gate-All-Around nanowire transistors

Content Provider	IEEE Xplore Digital Library
Author	Coquand, R. Monfray, S. Barraud, S. Samson, M.P. Arvet, C. Pradelles, J. Bustos, J. Martin, L. Tosti, L. Perreau, P. Hartmann, J.M. Lacord, J. Casse, M. Clement, L. Pofelski, A. Lepinay, K. Ghibaudo, G. Faynot, O. Poiroux, T. Boeuf, F. Skotnicki, T. De Salvo, B.
Copyright Year	2013
Description	Author affiliation: IMEP-LAHC, Grenoble, France (Ghibaudo, G.) \|\| STMicroelectron., Crolles, France (Coquand, R.; Monfray, S.; Samson, M.P.; Arvet, C.; Bustos, J.; Lacord, J.; Clement, L.; Pofelski, A.; Lepinay, K.; Boeuf, F.; Skotnicki, T.) \|\| LETI, CEA, Grenoble, France (Barraud, S.; Pradelles, J.; Martin, L.; Tosti, L.; Perreau, P.; Hartmann, J.M.; Casse, M.; Faynot, O.; Poiroux, T.; De Salvo, B.)
Abstract	This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal $SiO_{2}/Poly-Si:P$ gate stack and the first electrical results obtained with this technique are presented. The good nMOS performances $(I_{ON}=1mA/μm$ at $V_{G}=V_{T}+0.7V)$ with excellent electrostatics (SS down to 62mV/dec and DIBL below 10mV/V at $L_{G}=80nm)$ are paving the way to the ultimate CMOS architecture. To meet all requirements of low-power SoCs, we also demonstrate the feasibility of fabricating such devices with High-K Metal-Gate (HK-MG) stack and their possible co-integration with FDSOI structures.
Sponsorship	IEEE Electron Devices Soc.
File Size	1489565
File Format	PDF
ISBN	9781467352260
ISSN	21589682
e-ISBN	9784863483477
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-11
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP
Subject Keyword	Silicon Logic gates Silicon germanium Performance evaluation Very large scale integration Silicon compounds Lithography
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A solution for an ideal planar multi-gates process for ultimate CMOS?

High mobility w-gate nanowire P-FET on cSGOI substrates obtained by Ge enrichment technique

High-Performance High-$K$/Metal Planar Self-Aligned Gate-All-Around CMOS Devices

Ge gate-all-around FETs on Si

Notice of Retraction Analysis of parasitic bottom capacitance in n- and p-type Si-nanowire field effect transistors on bulk

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

Innovative through-Si 3D lithography for ultimate self-aligned planar Double-Gate and Gate-All-Around nanowire transistors

Similar Documents

A solution for an ideal planar multi-gates process for ultimate CMOS?

High mobility w-gate nanowire P-FET on cSGOI substrates obtained by Ge enrichment technique

High-Performance High-$K$/Metal Planar Self-Aligned Gate-All-Around CMOS Devices

Ge gate-all-around FETs on Si

Notice of Retraction Analysis of parasitic bottom capacitance in n- and p-type Si-nanowire field effect transistors on bulk

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

Innovative through-Si 3D lithography for ultimate self-aligned planar Double-Gate and Gate-All-Around nanowire transistors