NDLI: Open defects detection within 6T SRAM cells using a No Write Recovery Test Mode

Content Provider	IEEE Xplore Digital Library
Author	Josh Yang Baosheng Wang Ivanov, A.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada (Josh Yang; Baosheng Wang; Ivanov, A.)
Abstract	The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) technique that we refer to as No Write Recovery Test Mode (NWRTM) to detect all open defects, some of which produce Data Retention Faults (DRFs) but are undetectable by typical March tests. We demonstrate the effectiveness of our proposed technique by only applying it to fault-free memory cells and faulty cells with those undetectable defects but all the open defects are covered since our DFT technique is implemented by simply adding extra test cycles into typical March tests. Two 6T SRAM cell models, one a high-speed version and the other a low-power one, representing extreme cases according to traditional design methodologies, were designed to validate our proposed NWRTM at the circuit level. Simulation results show that our NWRTM amounts to a shorter total test time and improved open defect detection capability. In addition, in comparison to other DFT techniques, NWRTM requires the least additional design effort, and imply less area and no performance penalties.
Sponsorship	VLSI Soc. of India Minist. of Inf. and Commun. Technol., Gov. of India IEEE Electron Devices Soc. IEEE Circuits and Syst. Soc. Tata Consultancy Services Texas Instruments Inc. Nat. Semiconductor Intel Synopsys Cypress Semiconductor Corp. Infineon Technol. Cadence Conexant
Starting Page	493
Ending Page	498
File Size	289206
Page Count	6
File Format	PDF
ISBN	0769520723
DOI	10.1109/ICVD.2004.1260969
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-09
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Design for testability Circuit faults Fault detection Circuit testing Delay effects Design methodology Logic testing Circuit simulation Current supplies
Content Type	Text
Resource Type	Article

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