NDLI: Design and implementation of a parallel Verilog simulator: PVSim

Content Provider	IEEE Xplore Digital Library
Author	Tun Li Yang Guo Si-Kun Li
Copyright Year	2004
Description	Author affiliation: Nat. Univ. of Defense Technol., Changsha, China (Tun Li; Yang Guo; Si-Kun Li)
Abstract	Parallel HDL simulation is an efficient method to accelerate the verification process of large complex VLSI system design. This paper presents a parallel Verilog simulator-PVSim, which bases on optimistic asynchronous parallel simulation algorithm and MPI library. A new module-based simulation component mapping method is proposed. And an efficient module-based partition algorithm combined with pre-simulation partition algorithm is adopted. This paper introduces the architecture of PVSim, the Verilog component mapping techniques, the distributed simulation cycle arrangement and the circuit partition algorithm in detail. Experimental results show that PVSim can get promising speedup, as well as distributed workload and communication cost across processors.
Sponsorship	VLSI Soc. of India Minist. of Inf. and Commun. Technol., Gov. of India IEEE Electron Devices Soc. IEEE Circuits and Syst. Soc. Tata Consultancy Services Texas Instruments Inc. Nat. Semiconductor Intel Synopsys Cypress Semiconductor Corp. Infineon Technol. Cadence Conexant
Starting Page	329
Ending Page	334
File Size	309503
Page Count	6
File Format	PDF
ISBN	0769520723
DOI	10.1109/ICVD.2004.1260944
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-09
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Partitioning algorithms Circuit simulation Very large scale integration Digital systems Discrete event simulation Costs Process design System recovery Algorithm design and analysis
Content Type	Text
Resource Type	Article

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