NDLI: Impact of NBTI Induced Statistical Variation to SRAM Cell Stability

Content Provider	IEEE Xplore Digital Library
Author	La Rosa, G. Wee Loon Ng Rauch, S. Wong, R. Sudijono, J.
Copyright Year	2006
Description	Author affiliation: IBM Semicond. Res. & Dev. Center, East Fishkill, NY (La Rosa, G.)
Abstract	This work investigates the impact of negative bias temperature instability (NBTI) on the SRAM cell stability. As proposed by C. Wang et al., the stability of an SRAM cell can be determined by the peak current $(I_{CRIT})$ of the "N curve". In our experiments a typical NBTI stress was applied to one of the two pull up transistors part of an SRAM cell designed by using an advanced submicron CMOS technology. Both the mean and variance of the pMOSFET threshold voltage shift in saturation $(DeltaVt_{SAT})$ and the corresponding values of the ICRIT shifts $(DeltaI_{CRIT})$ were measured. An experimental correlation between the means and the variances of both parameters shifts was established and found consistent with the predicted simulated values in the case of $I_{CRIT}$ is degrading by only NBTI aging of the one or both pull up transistors. These results allow us to observe the direct impact of the NBTI shift of a pMOSFET transistor in a SRAM cell and the corresponding reduction to the static noise margin. In addition we propose, for the first time, a methodology to define a pMOSFET device NBTI target directly related to the SRAM cell stability and its dependence on SRAM design and the adopted CMOS technology. It is found that a more appropriate SRAM stability sensitive pMOSFET NBTI Vt $_{SAT}$ target cannot be limited to the $Vt_{SAT}$ mean shift, but needs as well a quantification of the allowed variance and initial SRAM $I_{CRIT}$ distribution
Starting Page	274
Ending Page	282
File Size	1736523
Page Count	9
File Format	PDF
ISBN	0780394984
DOI	10.1109/RELPHY.2006.251228
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Niobium compounds Titanium compounds Random access memory Stability CMOS technology MOSFET circuits Negative bias temperature instability Stress Transistors Threshold voltage
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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