NDLI: Reliability Characterization of Different Pore Sealing Techniques on Porous Silk Dielectric Films

Content Provider	IEEE Xplore Digital Library
Author	Michelon, J. Waeterloos, J. Bancken, P.H.L. Nguyen, V.H. Caluwaerts, R. Beyer, G. Rozeveld, S. Beach, E. Hoofman, R.J.O.M.
Copyright Year	2006
Description	Author affiliation: Philips Res., Leuven (Michelon, J.)
Abstract	As device dimensions scale down, the back-end-of-line dimensions scale down as well, which results in an increasing resistance-capacitance delay of the interconnect. In order to compensate for the increase in the capacitance part, porous low-k dielectrics have been introduced in copper interconnect technology. Due to the highly interconnected pore structure of most porous low-k materials, liquid and/or gaseous species fill the pores of the matrix during integration steps. In addition, pores give rise to surface roughness at the top-interface and at the sidewall after etch, which makes it difficult to deposit a thin, continuous barrier in narrow trenches embedded in porous low-k dielectrics. All of the above makes pore sealing a prerequisite for reliable porous low-k integration (Guedj et al., 2004). Different pore sealing techniques are under investigation. In the case of low-k materials in which the porosity is created using a porogen, the porosity creation could also be shifted to a later phase of the integration scheme; either after low-k etch (Caluwaerts et al., 2003) or after metal CMP (Fayole et al., 2004; Jousseaume et al., 2005), which is referred to as post-etch-burn-out (PEBO) and post-CMP-burn-out (PCBO), respectively. It has been demonstrated previously, that the dielectric reliability could be improved considerably by these kinds of pore sealing techniques (Tokei et al., 2004). In this paper, both integration approaches are compared for porous SiLKtrade dielectric resin (k=2.2) from The Dow Chemical Company and the effect of both integration approaches on the interline capacitance, the dielectric reliability and electromigration are investigated and discussed in more detail
Starting Page	496
Ending Page	501
File Size	1888032
Page Count	6
File Format	PDF
ISBN	0780394984
DOI	10.1109/RELPHY.2006.251268
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dielectric films Capacitance Dielectric materials Etching Delay Copper Transmission line matrix methods Rough surfaces Surface roughness Inorganic materials
Content Type	Text
Resource Type	Article

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