NDLI: The influence of deep trench and substrate resistance on the latchup robustness in a BiCMOS silicon germanium technology

Content Provider	IEEE Xplore Digital Library
Author	Voldman, S.H. Watson, A.
Copyright Year	2004
Description	Author affiliation: IBM Microeletronics, Essex Junction, VT, USA (Voldman, S.H.)
Abstract	This paper will demonstrate the effect of deep trench (DT) on the latchup robustness of an 0.13 /spl mu/m 200 GHz BiCMOS SiGeC HBT technology. Guard ring efficiency is evaluated using deep trench guard ring structures and compared to standard p+ and n-well guard ring structures. The latchup robustness is evaluated using pnpn structures with a deep trench perimeter on the edge of the well structure. Latchup robustness of pnpn structures is evaluated as a function of trench depth where the deep trench serves as a guard ring for the n-well region. Key latchup metrics, such as turn-on, trigger and sustaining voltage and current conditions, for a range of p+/n+ spacings as a function of trench depth, and external well and external substrate resistance is quantified. Trigger contours in a linear-logarithm space of trench depth and substrate resistance form a design space for optimization of latchup. Experimental results show that utilizing deep trench structure, and substrate contact spacing allows for latchup robustness in a low doped p-substrate wafer technology.
Starting Page	135
Ending Page	142
File Size	523833
Page Count	8
File Format	PDF
ISBN	078038315X
DOI	10.1109/RELPHY.2004.1315314
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-04-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Robustness BiCMOS integrated circuits Silicon germanium Germanium silicon alloys Current measurement Substrates Bipolar transistors Electrons Electric resistance Physics
Content Type	Text
Resource Type	Article

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