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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yanagawa, Y. Kobayashi, D. Ikeda, H. Saito, H. Hirose, K. |
| Copyright Year | 2007 |
| Description | Author affiliation: Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan (Yanagawa, Y.; Saito, H.) |
| Abstract | A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEL' soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET and SEL soft-error rates at each FF distributed in logic VLSI systems. A test chip is designed using a 0.2-mum fully-depleted silicon-on-insnlator standard cell library. The basic concepts have been validated with Verilog timing simulations. The cell-level implementation costs of the proposed scan FF are estimated to be reasonable. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 3940516 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424417049 |
| ISSN | 03796566 |
| DOI | 10.1109/RADECS.2007.5205569 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-09-10 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Flip-flops Very large scale integration Single event upset Logic testing Logic design System testing Libraries Hardware design languages Timing Costs integrated circuit radiation effects single event transient irradiation test logic VLSI system scan architecture |
| Content Type | Text |
| Resource Type | Article |
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