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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pratt, B. Caffrey, M. Carroll, J.F. Graham, P. Morgan, K. Wirthlin, M. |
| Copyright Year | 2007 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA (Pratt, B.; Carroll, J.F.; Wirthlin, M.) |
| Abstract | The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our Partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally until the specified percentage of resources are utilized. Thus the tool gives the maximum reliability gain for the specified area cost. The amount of mitigation applied can be chosen at a very fine level, giving the designer maximum flexibility when producing the final mitigated design. |
| Starting Page | 1 |
| Ending Page | 8 |
| File Size | 3788975 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424417049 |
| ISSN | 03796566 |
| DOI | 10.1109/RADECS.2007.5205468 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-09-10 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Costs Redundancy Circuits Software tools Laboratories Logic design Logic arrays Single event upset Protection |
| Content Type | Text |
| Resource Type | Article |
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