NDLI: Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime

Content Provider	IEEE Xplore Digital Library
Author	Xue Lin Yanzhi Wang Pedram, M.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA (Xue Lin; Yanzhi Wang; Pedram, M.)
Abstract	Sub/near-threshold computing has been proposed for ultra-low power applications. FinFET devices are considered as an alternative for bulk CMOS devices due to the superior characteristics, which make FinFET an excellent candidate for ultra-low power designs. In this paper, we first present an improved analytical FinFET model covering both sub- and near-threshold regimes. This model accurately captures the drain current as a function of both the gate and drain voltages. Based on the accurate FinFET model, we provide a detailed analysis on stack sizing of FinFET logic cells, and derive the optimal stack depth in FinFET circuits. We also provide a delay optimization framework for the FinFET circuits in the sub/near-threshold region, based on the stack sizing analysis. To the best of our knowledge, this is the first work that provides in-depth analysis of the stack sizing of FinFET logic cells in the sub/near-threshold region based on the accurate FinFET modeling. Experimental results on the 32nm Predictive Technology Model for FinFET devices demonstrate the effectiveness of the proposed optimization framework.
Starting Page	341
Ending Page	348
File Size	312183
Page Count	8
File Format	PDF
e-ISBN	9781479939466
DOI	10.1109/ISQED.2014.6783346
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates FinFETs Semiconductor device modeling Delays Threshold voltage stack sizing FinFET device sub/near-threshold
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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