NDLI: Predictive synchronization for DVFS-enabled multi-processor systems

Content Provider	IEEE Xplore Digital Library
Author	Buckler, M. Burleson, W.
Copyright Year	2014
Description	Author affiliation: AMD Res., Boxborough, MA, USA (Buckler, M.; Burleson, W.)
Abstract	Technology scaling has enabled the number of cores within a System on Chip to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. Typically, the interfaces between these clock domains experience multi-cycle latency due to their use of “brute force” synchronizers. Improvements in system performance can be achieved by replacing these brute force synchronizers with predictive synchronizers, which experience less than a cycle of latency. Unfortunately, the predictive synchronizers proposed so far require high power delay lines, rationally related clocks, or over a thousand cycles of latency for every change in frequency. Here we present a modified predictive synchronizer without these limitations. Our techniques allow for uninterrupted data flow during gradual frequency change and only a 20 cycle pause in data flow after an instant frequency change. In addition, we present an alternative clock domain interface which achieves less than a cycle of latency with an average 15% reduction in throughput.
Starting Page	270
Ending Page	275
File Size	507341
Page Count	6
File Format	PDF
e-ISBN	9781479939466
DOI	10.1109/ISQED.2014.6783336
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Synchronization Clocks Receivers Frequency-domain analysis Protocols Dynamic Voltage and Frequency Scaling Predictive Synchronizer Globally Asynchronous Locally Synchronous
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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