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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gong Chen Zhang Yu Bo Yang Qing Dong Nakatake, S. |
| Copyright Year | 2013 |
| Description | Author affiliation: Sch. of Environ. Eng., Univ. of Kitakyushu, Kitakyushu, Japan (Gong Chen; Zhang Yu; Bo Yang; Qing Dong; Nakatake, S.) |
| Abstract | In low power analog circuit designs, the current variation caused by the STI stress must be taken into account. In this paper, we address an energy trade-off related to the STI stress in the design of a comparator composed of the preamplifier and the conventional latch. The power consumption of the pre-amplifier can be formulated as a function of the diffusion length of MOSFETs when considering the STI stress. The longer diffusion length tends to make the power lower. On the other hand, the power to drive the latch is associated with the parasitic capacitance at the output of the pre-amplifier, so shorter diffusion is preferable. To cope with the trade-off, we provide the energy model of the comparator based on the geometric programming. In the post-layout HSPICE simulation with the STI BSIM model, we reveal that the impact of the STI stress on the energy becomes significant especially in low power designs. |
| Sponsorship | IEEE Electron Devices Soc. |
| Starting Page | 585 |
| Ending Page | 590 |
| File Size | 1964506 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467349512 |
| ISSN | 19483287 |
| e-ISBN | 9781467349536 |
| DOI | 10.1109/ISQED.2013.6523670 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-03-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Stress Latches Semiconductor device modeling Logic gates Noise measurement |
| Content Type | Text |
| Resource Type | Article |
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