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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nassif, S.R. Gi-Joon Nam Banerjee, S. |
| Copyright Year | 2013 |
| Description | Author affiliation: IBM Res., Austin, TX, USA (Nassif, S.R.; Gi-Joon Nam) || IBM Res., East Fishkill, NY, USA (Banerjee, S.) |
| Abstract | Current technology scaling trends are changing the character of wire delay variability. The distribution of wire delay is asymmetric, with a long positive tail which can be as much as 2X longer than the negative tail. This is due to the geometry of these wires, where the aspect ratio is biased towards tall thin wire cross-sections, as well as manufacturing induced variations particularly from lithography. These trends are important for timing closure, whether done via corner-based or statistical analysis. In this paper, we explore these trends, demonstrate their impact in a modern 32nm CMOS design, and suggest ways in which this trend can be managed and reduced. Particularly, through physical synthesis optimization on industrial designs, we show how these trends/observations can be utilized to produce more reliable designs. As the interconnect scaling lags behind the device scaling, the importance of wire variability will grow further in the future technology nodes. |
| Sponsorship | IEEE Electron Devices Soc. |
| Starting Page | 591 |
| Ending Page | 596 |
| File Size | 559996 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467349512 |
| ISSN | 19483287 |
| e-ISBN | 9781467349536 |
| DOI | 10.1109/ISQED.2013.6523671 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-03-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wires Delays Metals Market research Integrated circuit interconnections |
| Content Type | Text |
| Resource Type | Article |
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