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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Qiaosha Zou Jing Xie Yuan Xie |
| Copyright Year | 2013 |
| Description | Author affiliation: Pennsylvania State Univ., University Park, PA, USA (Qiaosha Zou; Jing Xie; Yuan Xie) |
| Abstract | Three-dimensional integrated circuit (3D IC) is a promising solution to continue the performance scaling. However, the fabrication cost for 3D ICs can be a major concern for the adoption of this emerging technology. In this paper, we study the cost implication for both TSV-based and interposer-based 3D ICs, with the observation that many long metal interconnects in 2D designs are replaced by TSVs in 3D designs, and therefore the number of metal layers to satisfy routing requirements can be reduced, resulting in cost saving in 3D ICs. Based on our cost model, we propose a cost-driven 3D design space optimization flow that balances the design area and metal layer requirement, by optimizing the cost tradeoffs between silicon area and the number of metal layers. With the cost-driven design optimization flow, we can achieve cost saving up to 19% for TSV-based 3D designs, and 26% for interposer-based 3D designs, respectively, compared to the baseline designs. |
| Sponsorship | IEEE Electron Devices Soc. |
| Starting Page | 294 |
| Ending Page | 299 |
| File Size | 410314 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467349512 |
| ISSN | 19483287 |
| e-ISBN | 9781467349536 |
| DOI | 10.1109/ISQED.2013.6523625 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-03-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Three-dimensional displays Metals Stacking Routing Logic gates Through-silicon vias Bonding |
| Content Type | Text |
| Resource Type | Article |
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