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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yue Fu Hei Wong Liou, J.J. |
| Copyright Year | 2005 |
| Description | Author affiliation: Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816, USA. (Yue Fu) |
| Abstract | The noise behaviors of the junction field-effect transistor (JFET) fabricated with self-aligned planer technology are studied. The device structure being considered has a wide separation between source-gate and drain-gate with a shallow trench isolation (STI) technique. High noise level is found in the devices with STI and the normalized drain noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated in the STI regions and a model is developed to explain the bias dependence of the noise characteristics. To reduce the noise level, the STI region should be kept small and better oxidation technique should be employed for the STI passivation. |
| Starting Page | 39 |
| Ending Page | 42 |
| File Size | 1968959 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780393392 |
| DOI | 10.1109/EDSSC.2005.1635200 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-12-19 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Low-frequency noise FETs Metalworking machines Semiconductor device noise Noise level Integrated circuit noise Noise generators Isolation technology Low-noise amplifiers Noise measurement shallow trench isolation JFET self-aligned modeling |
| Content Type | Text |
| Resource Type | Article |
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