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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Annamalai, A. Kumar, R. Vijayakumar, A. Kundu, S. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Massachusetts Amherst, Amherst, MA, USA (Annamalai, A.; Kumar, R.; Vijayakumar, A.; Kundu, S.) |
| Abstract | As conventional CMOS technology is approaching scaling limits, the shift in trend towards stacked 3D Integrated Circuits (3D IC) is gaining more importance. 3D ICs offer reduced power dissipation, higher integration density, heterogeneous stacking and reduced interconnect delays. In a 3D IC stack, all but the bottom tier are thinned down to enable through-silicon vias (TSV). However, the thinning of the substrate increases the lateral thermal resistance resulting in higher intra-layer temperature gradients potentially leading to performance degradation and even functional errors. In this work, we study the effect of thinning the substrate on temperature profile of various tiers in 3D ICs. Our simulation results show that the intra-layer temperature gradient can be as high as 57°C. Often, the conventional static solutions lead to highly inefficient design. To this end, we present a system-level situation-aware integrated scheme that performs opportunistic thread migration and dynamic voltage and frequency scaling (DVFS) to effectively manage thermal violations while increasing the system throughput relative to stand-alone schemes. |
| Sponsorship | IEEE Electron Devices Soc. |
| Starting Page | 88 |
| Ending Page | 95 |
| File Size | 1579415 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781467349512 |
| ISSN | 19483287 |
| e-ISBN | 9781467349536 |
| DOI | 10.1109/ISQED.2013.6523595 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-03-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Registers Integrated circuits Substrates Thermal analysis Switches spatial gradient 3D IC dynamic Thermal Management dynamic voltage and frequency scaling (DVFS) thread migration |
| Content Type | Text |
| Resource Type | Article |
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