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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Salahuddin, S.M. Hailong Jiao Kursun, V. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China (Salahuddin, S.M.; Hailong Jiao; Kursun, V.) |
| Abstract | A new FinFET memory circuit technique based on asymmetrically gate underlap engineered bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline access transistors are weakened during read operations while enhanced during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability and write ability are both enhanced by up to 6.12x and 58%, respectively, without causing any area overhead as compared to the standard symmetrical six-FinFET SRAM cells in a 15nm FinFET technology. The leakage power consumption is also reduced by up to 96.5% with the proposed asymmetrical FinFET SRAM cell as compared to the standard six-FinFET SRAM cells with symmetrical bitline access transistors. |
| Sponsorship | IEEE Electron Devices Soc. |
| Starting Page | 353 |
| Ending Page | 358 |
| File Size | 1304957 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467349512 |
| ISSN | 19483287 |
| e-ISBN | 9781467349536 |
| DOI | 10.1109/ISQED.2013.6523634 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-03-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Random access memory FinFETs Noise CMOS integrated circuits Abstracts leakage power consumption Memory data stability on-die cache asymmetrical gate underlap engineering static noise margin write margin |
| Content Type | Text |
| Resource Type | Article |
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