NDLI: TSV and DFT cost aware circuit partitioning for 3D-SOCs

Content Provider	IEEE Xplore Digital Library
Author	Kumar, A. Reddy, S.M. Pomeranz, I. Becker, B.
Copyright Year	2012
Description	Author affiliation: School of Electrical and Computer Eng., Purdue University, W. Lafayette, IN, 47907, USA (Pomeranz, I.) \|\| Institute for Computer Sci. Albert Ludwigs University Freiburg, 79110, Germany (Becker, B.) \|\| Electrical and Computer Eng. Dept., University of Iowa, Iowa City, IA 52242, USA (Kumar, A.; Reddy, S.M.)
Abstract	3D-SOC technology has significant performance and power gains over 2D as interconnects can be shortened significantly. To accrue full benefits of reduced interconnect lengths large designs need to be partitioned into several dies. In this work we propose a hypergraph based multi-objective circuit partitioning scheme for 3D-SOCs that simultaneously reduces the number of inter die connections, which use through silicon vias (TSVs), and reduces additional DFT logic needed for pre-bond test of dies. An Ordered Block hypergraph partitioning scheme is proposed to achieve these objectives. Experimental results on several industrial circuits demonstrate the effectiveness of the proposed approach.
Starting Page	21
Ending Page	26
File Size	892629
Page Count	6
File Format	PDF
ISBN	9781467310345
ISSN	19483287
e-ISBN	9781467310369
DOI	10.1109/ISQED.2012.6187469
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Partitioning algorithms Discrete Fourier transforms Merging System-on-a-chip Integrated circuit modeling Logic gates
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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