NDLI: Methodology for analysis of TSV stress induced transistor variation and circuit performance

Content Provider	IEEE Xplore Digital Library
Author	Li Yu Wen-Yao Chang Kewei Zuo Wang, J. Yu, D. Boning, D.
Copyright Year	2012
Description	Author affiliation: Taiwan Semiconductor Manufacturing Company, Ltd. (Wen-Yao Chang; Kewei Zuo; Wang, J.; Yu, D.) \|\| Microsystems Technology Laboratories, Massachusetts Institute of Technology (Li Yu; Boning, D.)
Abstract	As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach.
Starting Page	216
Ending Page	222
File Size	1746409
Page Count	7
File Format	PDF
ISBN	9781467310345
ISSN	19483287
e-ISBN	9781467310369
DOI	10.1109/ISQED.2012.6187497
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Stress Transistors Silicon Threshold voltage Layout Finite element methods
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Electromigration induced stress in through-silicon-via (TSV)

TSV stress-aware performance and reliability analysis

Development and application of a micro-infrared photoelasticity system for stress evaluation of through-silicon Vias (TSV)

Simulation methodology and flow integration for 3D IC stress management

TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

Experimental and finite elemental investigations on residual stress of TSV

Experimental and finite elemental investigations on residual stress of TSV

Finite element stress analysis of 3D TSV stack subject to large temperature loading

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Methodology for analysis of TSV stress induced transistor variation and circuit performance

Similar Documents

Electromigration induced stress in through-silicon-via (TSV)

TSV stress-aware performance and reliability analysis

Development and application of a micro-infrared photoelasticity system for stress evaluation of through-silicon Vias (TSV)

Simulation methodology and flow integration for 3D IC stress management

TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

Experimental and finite elemental investigations on residual stress of TSV

Experimental and finite elemental investigations on residual stress of TSV

Finite element stress analysis of 3D TSV stack subject to large temperature loading

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Methodology for analysis of TSV stress induced transistor variation and circuit performance