NDLI: Low complexity cross parity codes for multiple and random bit error correction

Content Provider	IEEE Xplore Digital Library
Author	Poolakkaparambil, M. Mathew, J. Jabir, A.M. Mohanty, S.P.
Copyright Year	2012
Description	Author affiliation: Department of Computer Science, University of Bristol, UK (Mathew, J.) \|\| Department of Computer Science and Engineering, University of North Texas, USA (Mohanty, S.P.) \|\| Department of Computer Science and Electronics, Oxford Brookes University, UK (Poolakkaparambil, M.; Jabir, A.M.)
Abstract	Error detection and correction which has been used in communication and memory design is becoming increasingly important in fault tolerant logic circuit design. As a result of the aggressive technology scaling, the current high-density integrated circuits are easily succumbed to faulty operations generated from many sources including stuck-at-faults, radiation induced faults, or malicious eavesdropper attacks. The currently used techniques like low-density parity-check (LDPC) and Hamming code based fault masking to mitigate bit flips in the digital circuits are either single bit error correcting or multiple error correctable with Bose-Choudhury-Hocquenghem (BCH) and Reed-solomon based methods with very large overheads. This paper introduce a novel cross code based method that can correct multiple errors with minimal compromise in error correction capability and area. The key idea of the novel method proposed in this paper is that do not correct all the errors but minimize their probability being escaped. Experimental results of the proposed methods show that the following: (1) area overhead is 101% for Hamming cross code and 106% for BCH cross code for a 90-bit finite field multiplier and (2) 150% for Hamming cross code and 170% for BCH cross codes for practically used 163-bit digit serial polynomial basis multiplier. Thus, the proposed methods are significantly efficient compared to Triple Modular Redundancy (TMR), LDPC, Hamming based methods in terms of area overhead and also the first attempted approach to a low complexity multiple error correctable digit serial multiplier to the best of the authors knowledge.
Starting Page	57
Ending Page	62
File Size	1234979
Page Count	6
File Format	PDF
ISBN	9781467310345
ISSN	19483287
e-ISBN	9781467310369
DOI	10.1109/ISQED.2012.6187474
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error correction codes Transient analysis Decoding Error correction Cryptography Complexity theory Circuit faults Bose-Choudhury-Hocquenghem Code Polynomial Basis Bultiplier Concurrent Error Detection Single Error Correction N-Modular Redundancy
Content Type	Text
Resource Type	Article

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