NDLI: Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew

Content Provider	IEEE Xplore Digital Library
Author	Tawfik, S.A. Kursun, V.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI (Tawfik, S.A.; Kursun, V.)
Abstract	A methodology based on supply voltage scaling for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock signal is distributed globally at a lower optimum supply voltage. To maintain the speed of the system, a dual supply voltage $(dual-V_{DD})$ clock distribution network is presented. Level converters are utilized to restore the standard full swing clock signal at the leaves of the low voltage clock distribution network. A novel level converter with low skew, propagation delay, and power consumption characteristics is presented. The optimum supply voltage that minimizes clock skew is 44% lower than the nominal supply voltage in a 0.18mum CMOS technology. The temperature fluctuations induced skew and power consumption of the proposed $dualdual-V_{DD}$ clock distribution network are 74% and 50.8% lower, respectively, as compared to a standard clock distribution network operating at the nominal supply voltage
Starting Page	73
Ending Page	78
File Size	215783
Page Count	6
File Format	PDF
ISBN	0769527957
DOI	10.1109/ISQED.2007.65
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-03-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Temperature distribution Fluctuations Energy consumption CMOS technology Circuits Threshold voltage Power system restoration Signal restoration Propagation delay
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew

Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement

Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew

Low-swing clock domino logic incorporating dual supply and dual threshold voltages

Dual signal frequencies and voltage levels for low power clock distribution using thyristor delay

Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits

Leakage power optimization for clock network using dual-Vth technology

Clock skew optimization considering complicated power modes

Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew

Similar Documents

Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew

Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement

Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew

Low-swing clock domino logic incorporating dual supply and dual threshold voltages

Dual signal frequencies and voltage levels for low power clock distribution using thyristor delay

Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits

Leakage power optimization for clock network using dual-Vth technology

Clock skew optimization considering complicated power modes

Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew