NDLI: A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays

Content Provider	IEEE Xplore Digital Library
Author	Drego, N. Chandrakasan, A. Boning, D.
Copyright Year	2007
Description	Author affiliation: Microsystems Technol. Labs., MIT, Cambridge, MA (Drego, N.; Chandrakasan, A.; Boning, D.)
Abstract	A test-structure comprising a dual-slope integrating analog-to-digital converter, auto-zeroing circuitry, digital control logic and a large array of devices under test (DUTs) has been developed to isolate threshold voltage variation. Threshold-voltage $(V_{T})$ isolation is achieved by testing all DUTs in the subthreshold regime where drain-to-source current is an exponential function of $V_{T}.$ Spice simulations show that the structure is at least an order of magnitude more sensitive to $V_{T}$ variation than to channel length variation. This, in combination with a hierarchical access scheme and leakage control system, allows efficient characterization of $DeltaV_{T}$ for ~70,000 NMOS and ~70,000 PMOS devices in a dense 2mm times 2mm DUT array
Starting Page	281
Ending Page	286
File Size	467672
Page Count	6
File Format	PDF
ISBN	0769527957
DOI	10.1109/ISQED.2007.24
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-03-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Circuit testing Logic testing Logic arrays MOS devices Analog-digital conversion Digital control Logic devices Logic circuits Threshold voltage
Content Type	Text
Resource Type	Article

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