NDLI: An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs

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Fifteenth International Symposium on Quality Electronic Design

International Symposium on Quality Electronic Design (ISQED)

Thirteenth International Symposium on Quality Electronic Design (ISQED)

2011 12th International Symposium on Quality Electronic Design

2010 11th International Symposium on Quality Electronic Design (ISQED)

2009 10th International Symposium on Quality Electronic Design

9th International Symposium on Quality Electronic Design (isqed 2008)

8th International Symposium on Quality Electronic Design (ISQED'07)

8th International Symposium on Quality Electronic Design-Title

8th International Symposium on Quality Electronic Design-Copyright

Technical Sub-Committees

Steering Committee

Advisory Committee

Best Paper Selection Committee

Conference at a Glance

SUB-45nm Technology and Design Challenges

Multi-Gate MOSFET Design

SUB 45nm Low Power Design Challenges

Self-Adaptive Systems to Drive out the Nano-Scale Devil

Quality Driven Manufacturing and SOC Designs

DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield

DFT and Test: Ensuring Product Quality

Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs

DFM--EDA's Salvation or its Excuse for Being out of Touch with Engineering?

Tipping Point for New Design Technologies: DFM, Low Power and ESL

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation

Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS

Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs

A New Simulation Method for NBTI Analysis in SPICE Environment

Combating NBTI Degradation via Gate Sizing

Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability

A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers

Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew

Speculative Energy Scheduling for LDPC Decoding

Dynamic Power Management by Combination of Dual Static Supply Voltages

Low Voltage Buffered Bandgap Reference

A DLL Based Multiphase Hysteretic DC-DC Converter

Statistical Timing Analysis Considering Spatial Correlations

Systematic Design of a Flash ADC for UWB Applications

EDA to the Rescue of the Silicon Roadmap

Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions

FinFET Based SRAM Design for Low Standby Power Applications

Compact Modeling of a PD SOI MESFET for Wide Temperature Designs

Modeling of PMOS NBTI Effect Considering Temperature Variation

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI

A Low-Power Multi-Pin Maze Routing Methodology

An Aggregation-Based Algebraic Multigrid Method for Power Grid Analysis

Design and Analysis of "Tree+Local Meshes" Clock Architecture

An Efficient Algorithm for RLC Buffer Insertion

Fast Crosstalk Repair by Quick Timing Change Estimation

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

Cross Layer Error Exploitation for Aggressive Voltage Scaling

A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems

Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems

A Unified Optimal Voltage Selection Methodology for Low-Power Systems

Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion

A 8b 10Ms/s Low Power Pipelined A/D Converter

First-Order Continuous-Time Sigma-Delta Modulator

Reducing EPL Alignment Errors for Large VLSI Layouts

Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS

Efficient Signal Integrity Verification of Multi-Coupled Transmission Lines with Asynchronously Switching Non-Linear Drivers

Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals

Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations

Tests on Symmetry and Continuity between BSIM4 and BSIM5

Interface Specification Assurance Methods

Multi-Dimensional Circuit and Micro-Architecture Level Optimization

A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays

Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits

Processing High Volume Scan Test Results for Yield Learning

Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture

Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits

Inductive Fault Analysis for Test and Diagnosis of DNA Sensor Arrays

Fine-Grained Redundancy in Adders

MEMS Failure Probability Prediction and Quality Enhancement Using Neural Networks

Variation Aware Timing Based Placement Using Fuzzy Programming

Variation Analysis of CAM Cells

Design-for-Manufacture for Multi Gate Oxide CMOS Process

Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure

Power Delivery Aware Floorplanning for Voltage Island Designs

Passive Modeling of Interconnects by Waveform Shaping

A Power Network Synthesis Method for Industrial Power Gating Designs

Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint

Challenges in Evaluations for a Typical-Case Design Methodology

SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs

Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors

A High Frequency PWM Controller in HV Bi-CMOS Process Considering SOI Self-Heating

Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis

Built-In Test of RF Mixers Using RF Amplitude Detectors

Glitch Control with Dynamic Receiver Threshold Adjustment

Programmable High Speed Multi-Level Simultaneous Bidirectional I/O

A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations

Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect Characterization

System Level Estimation of Interconnect Length in the Presence of IP Blocks

Energy-Minimization Model for Fill Synthesis

On-Chip Inductance in X Architecture Enabled Design

Impact of Variability on Clock Skew in H-tree Clock Networks

A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances

SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design

Pareto-Front Computation and Automatic Sizing of CPPLLs

InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization

Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model

Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications

High-Frequency-Measurement-Based Frequency-Variant Transmission Line Characterization and Circuit Modeling for Accurate Signal Integrity Verification

Achieving Low-Cost Linearity Test and Diagnosis of \Sigma \Delta ADCs via Frequency-Domain Nonlinear Analysis and Macromodeling

Fully Digital Optimized Testing and Calibration Technique for \Sigma \Delta ADC's

Cell-Based Semicustom Design of Zigzag Power Gating Circuits

Lookup Table-Based Adaptive Body Biasing of Multiple Macros

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM

A High Performance, Scalable Multiplexed Keeper Technique

On-Line Adjustable Buffering for Runtime Power Reduction

Programmable Engines for Embedded Systems: The New Challenges

Soft-Errors Phenomenon Impacts on Design for Reliability Technologies

Forging Tighter Connections Between Design and Manufacturing in the Nanometer Age

3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method

Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design

Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology

A Design Methodology for Matching Improvement in Bandgap References

Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs

Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis

Transistor-Level Synthesis for Low-Power Applications

Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis

Self-Timed Regenerators for High-Speed and Low-Power Interconnect

Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization

General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits

Investigating Crosstalk in Sub-Threshold Circuits

A Model for Timing Errors in Processors with Parameter Variation

Parameter-Variation-Aware Analysis for Noise Robustness

Future Prediction of Self-Heating in Short Intra-Block Wires

Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model

Do Digital Design and Variability Mix like Oil and Water?

An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization

From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis

Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below

A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology

Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy

Small-Delay Defect Detection in the Presence of Process Variations

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture

On Accelerating Soft-Error Detection by Targeted Pattern Generation

Enhanced Identification of Strong Robustly Testable Paths

Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction

Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance

Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders

Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration

Designing and Validating Process-Variation-Aware Cell Libraries

Transferring Optical Proximity Correction (OPC) Effect into Optical Mode

OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts

An Automated and Fast OPC Algorithm for OPC-Aware Layout Design

A New Method of Implementing Hierarchical OPC

A New Flexible Algorithm for Random Yield Improvement

Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations

Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm

Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques

Redundant Via Insertion in Restricted Topology Layouts

Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement

Congestion Driven Buffer Planning for X-Architecture

Probabilistic Congestion Prediction with Partial Blockages

OPC-Friendly Bus Driven Floorplanning

Power-Gating Aware Floorplanning

Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs

An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs

Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations

Virtual Channels Planning for Networks-on-Chip

A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits

MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits

An SEU-Tolerant Programmable Frequency Divider

A TMR Scheme for SEU Mitigation in Scan Flip-Flops

Variation Impact on SER of Combinational Circuits

MEMESTAR: A Simulation Framework for Reliability Evaluation over Multiple Environments

Participating organizations

ISQED07 Best Papers [3 awards]

ISQED 2008 Call for Papers

7th International Symposium on Quality Electronic Design (ISQED'06)

Sixth international symposium on quality electronic design (isqed'05)

International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.

Proceedings International Symposium on Quality Electronic Design

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)

An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs

Content Provider	IEEE Xplore Digital Library
Author	Bhojwani, P. Mahapatra, R.N.
Copyright Year	2007
Description	Author affiliation: Dept. of Comput. Sci., Texas A&M Univ., College Station, TX (Bhojwani, P.; Mahapatra, R.N.)
Abstract	To address the reliability concerns that affect the lifetime of complex systems-on-a-chip (SoC) designs, a concurrent on-line SoC test scheme is essential to circumvent the prohibitive costs - test time and test power $associated with off-line SoC test. A test infrastructure IP (TI-IP) is deployed within the network-on-chip (NoC) based SoC design to provide on-line test support while managing the intrusion of test into the executing applications within the system. This research describes the architecture and operation of a TI-IP capable of testing SoCs and demonstrates its operation in two SoC test configurations developed using research domain application and test benchmarks
Starting Page	867
Ending Page	872
File Size	280401
Page Count	6
File Format	PDF
ISBN	0769527957
DOI	10.1109/ISQED.2007.35
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-03-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network-on-a-chip System testing System-on-a-chip Life testing Power system reliability Costs Power system management Energy consumption Energy management Runtime
Content Type	Text
Resource Type	Article

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