NDLI: Timing yield estimation from static timing analysis

Content Provider	IEEE Xplore Digital Library
Author	Gattiker, A. Nassif, S. Dinakar, R. Long, C.
Copyright Year	2001
Description	Author affiliation: IBM Austin Res. Lab., TX, USA (Gattiker, A.)
Abstract	This paper presents a means for estimating parametric timing yield and guiding robust design for-quality in the presence of manufacturing and operating environment variations. Dual emphasis is on computational efficiency and providing meaningful robust-design guidance. Computational efficiency is achieved by basing the proposed methodology on a post-processing step applied to the report generated as a by-product of static timing analysis. Efficiency is also ensured by exploiting the fact that for small processing/environment variations, a linear model is adequate for capturing the resulting delay change. Meaningful design guidance is achieved by analyzing the timing-related influence of variations on a path-by-path basis, allowing designers perform a quality-oriented design pass focused on key paths. A coherent strategy is provided to handle both die-to-die and within-die variations. Examples from a PowerPC microprocessor illustrate the methodology and its capabilities.
Sponsorship	IEEE Tech. Committee on VLSI Design (TCVLSI)
Starting Page	437
Ending Page	442
File Size	560757
Page Count	6
File Format	PDF
ISBN	0769510256
DOI	10.1109/ISQED.2001.915268
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-03-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Yield estimation Delay estimation Circuit simulation Robustness Pulp manufacturing Microprocessors Fluctuations Temperature Dielectrics
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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