NDLI: Defect-oriented fault simulation and test generation in digital circuits

Content Provider	IEEE Xplore Digital Library
Author	Kuzmicz, W. Pleskacz, W. Raik, J. Ubar, R.
Copyright Year	2001
Description	Author affiliation: Warsaw Univ. of Technol., Poland (Kuzmicz, W.)
Abstract	A generalized approach is presented to fault simulation and test generation based on a uniform functional fault model for different system representation levels. The fault model allows one to represent the defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generalized differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for higher level fault simulation purposes. In such a way, the functional fault model can be regarded as an interface for mapping faults from one system level to another, helping to carry out hierarchical fault simulation and test generation in digital systems. A methodology is proposed which allows one to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. Experimental data of the hierarchical defect-oriented simulation for ISCAS'85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation based on counting defects without considering defect probabilities may lead to a considerable overestimation of the result.
Sponsorship	IEEE Tech. Committee on VLSI Design (TCVLSI)
Starting Page	365
Ending Page	371
File Size	698068
Page Count	7
File Format	PDF
ISBN	0769510256
DOI	10.1109/ISQED.2001.915257
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-03-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit testing Circuit simulation System testing Communication networks Differential equations Digital systems Electrical fault detection Fault detection Benchmark testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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