NDLI: On accumulator-based bit-serial test response compaction schemes

Content Provider	IEEE Xplore Digital Library
Author	Bakalis, D. Nikolos, D. Vergos, H.T. Kavousianos, X.
Copyright Year	2001
Description	Author affiliation: Dept. of Comput. Eng. & Inf., Patras Univ., Greece (Bakalis, D.)
Abstract	The data paths of most contemporary general and special purpose processors include registers, adders and other arithmetic circuits. If these circuits are also used for built-in self-test, the extra area required for embedding testing structures can be cut down efficiently. Several schemes based on accumulators, subtracters, multipliers and shift, resisters have been proposed and analyzed in the past for parallel test response compaction, whereas some efforts have also been devoted in the bit-serial response compaction case. In this paper, we analyse and evaluate the bit-serial version of a recently proposed scheme for parallel test response compaction. Experimental results on the ISCAS'85 benchmark circuits indicate that the post-compaction fault coverage drop attained by the new scheme is significantly lower than other already known accumulator-based compaction schemes.
Sponsorship	IEEE Tech. Committee on VLSI Design (TCVLSI)
Starting Page	350
Ending Page	355
File Size	608022
Page Count	6
File Format	PDF
ISBN	0769510256
DOI	10.1109/ISQED.2001.915255
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-03-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Compaction Circuit testing Circuit faults Built-in self-test Test pattern generators Adders Automatic testing Design for testability Integrated circuit testing Registers
Content Type	Text
Resource Type	Article

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