NDLI: Analog CMOS/SOI with NMOS-SOI-depletion transistors

Content Provider	IEEE Xplore Digital Library
Author	Dingwall, A.G.F. Hsueh, F.-L. Hsu, S.T.
Copyright Year	1989
Description	Author affiliation: David Sarnoff Res. Center, Princeton, NJ, USA (Dingwall, A.G.F.; Hsueh, F.-L.; Hsu, S.T.)
Abstract	Summary form only given. Improved analog/SOI A/D converter and opamp performance results were obtained by adding normally-on NMOS-depletion transistors to a standard CMOS/SOS process. The improvement results in part from the low RC time constant substrate tie associated with the structure. Dynamic control of substrate potential (a component of threshold voltage) is important for high-speed processing of millivolt level analog signals. Other advantages are: (1) reduced voltage drop across depletion transistors, allowing wider signal swing and/or reduced operating voltage; (2) higher currents from small, lower-capacitance transistors; (3) superior gain characteristics in saturation; and (4) new circuit options possible with N-depletion transistors.
Starting Page	107
Ending Page	108
File Size	121455
Page Count	2
File Format	PDF
DOI	10.1109/SOI.1989.69789
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOS devices Threshold voltage Bandwidth Impedance CMOS process Voltage control Signal processing Capacitance Circuits Atomic layer deposition
Content Type	Text
Resource Type	Article

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