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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Doris, B.B. Hook, T. |
| Copyright Year | 2015 |
| Description | Author affiliation: IBM Res. T. J. Watson Res. Center, Yorktown Heights, NY, USA (Doris, B.B.; Hook, T.) |
| Abstract | Conventional planar transistors have been used throughout the semiconductor industry for the past several decades. Further miniaturization of conventional devices has been proven to be a significant challenge and thus the industry has transitioned to Planar Fully Depleted FETs and FinFETs. As we look out at technologies beyond 7nm node there are many barriers which appear to limit the scalability of FinFETs. Therefore it is important to consider the device architecture options that can serve as a replacement and enable further scaling to meet future technology requirements. This invited talk discusses the scalability of Fully Depleted FETs and FinFETs and also proposes options to enable continued scaling beyond 7nm node. |
| Starting Page | 160 |
| Ending Page | 163 |
| File Size | 751819 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467371339 |
| ISSN | 19308876 |
| e-ISBN | 9781467371353 |
| DOI | 10.1109/ESSDERC.2015.7324738 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-09-14 |
| Publisher Place | Austria |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Electrostatics Performance evaluation Silicon Wires Strain Transistors (key words) Conventional device architecture Fully Depleted devices FinFETs novel devices transistor scaling |
| Content Type | Text |
| Resource Type | Article |
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