NDLI: Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

Content Provider	IEEE Xplore Digital Library
Author	Faynot, O. Andrieu, F. Weber, O. Fenouillet-Béranger, C. Perreau, P. Mazurier, J. Benoist, T. Rozeau, O. Poiroux, T. Vinet, M. Grenouillet, L. Noel, J.-P. Posseme, N. Barnola, S. Martin, F. Lapeyre, C. Cassé, M. Garros, X. Jaud, M.-A. Thomas, O. Cibrario, G. Tosti, L. Brevard, L. Tabone, C. Gaud, P. Barraud, S. Ernst, T. Deleonibus, S.
Copyright Year	2010
Description	Author affiliation: CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France (Faynot, O.; Andrieu, F.; Weber, O.; Fenouillet-Béranger, C.; Perreau, P.; Mazurier, J.; Benoist, T.; Rozeau, O.; Poiroux, T.; Vinet, M.; Grenouillet, L.; Noel, J.-P.; Posseme, N.; Barnola, S.; Martin, F.; Lapeyre, C.; Cassé, M.; Garros, X.; Jaud, M.-A.; Thomas, O.; Cibrario, G.; Tosti, L.; Brevard, L.; Tabone, C.; Gaud, P.; Barraud, S.; Ernst, T.; Deleonibus, S.)
Abstract	Recent device developments and achievements have demonstrated that planar undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. We have proven this planar option to be easier to integrate than the non planar devices like FinFET. This paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed. Electrostatic integrity, drivability, within wafer variability and scalability are addressed through silicon data (down to 18nm gate length) and TCAD analyses. Solutions to the Multiple VT challenges and non logic devices (ESD, I/Os) are also reported.
File Size	670474
File Format	PDF
ISBN	9781442474185
ISSN	2156017X
e-ISBN	9781424474202
e-ISBN	9781424474196
DOI	10.1109/IEDM.2010.5703287
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Performance evaluation Electrostatics FinFETs Scalability Materials
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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