NDLI: Table of contents

Please wait, while we are loading the content...

2015 45th European Solid State Device Research Conference (ESSDERC)

Table of contents

5G wireless communication beyond 2020

Theoretical analyses and modeling for nanoelectronics

Nature as microelectronic fab: Bioelectronics: Materials, transistors and circuits

New frontiers in digital health: Remote monitoring of animal and human metabolism on our smartphones and tablets

Ge/III-V MOS device technologies for low power integrated systems

Investigations of vapor phase deposited transition metal dichalcogenide films for future electronic applications

High performance NEMS devices for sensing applications

Computational electronics for the $21^{st}$ century: Reflections on the past, present, and future

Compact modeling of DG-Tunnel FET for Verilog-A implementation

Modeling of the conduction characteristics of voltage-driven bipolar RRAMs including turning point effects

A surface potential and current model for polarity-controllable silicon nanowire FETs

Mixed-domain compact modeling framework for fluid flow driven by electrostatic organic actuators

Charge trapping in gate-drain access region of AlGaN/GaN MIS-HEMTs after drain stress

E-mode AlGaN/GaN True-MOS, with high-k ZrO gate insulator

Technology and design of GaN power devices

Experimental analysis of planar edge terminations for high voltage 4H-SiC devices

On the fly characterization of charge trapping phenomena at GaN/dielectric and GaN/AlGaN/dielectric interfaces using impedance measurements

UTBB FDSOI: Evolution and opportunities

Implementation of $ARM^{®}$ Cores in FinFET technolgies

FinFET versus UTBB SOI — A RF perspective

Antenna-coupled single-metal thermocouple array for energy harvesting

Novel CMOS-compatible a-Si based oscillator and threshold switch

Modelling and simulation of nanomagnetic logic with cadence virtuoso using Verilog-A

Non-boolean computing based on linear waves and oscillators

Plasmonic and electronic device integrated circuits and their characteristics

Emerging nonvolatile memory (NVM) technologies

Optimization of the write algorithm at low-current (10μA) in Cu/Al-based conductive-bridge RAM

On the voltage scaling potential of SONOS non-volatile memory transistors

High performance low A/R poly PN diode for 20nm node PCRAM cell switch

The world's first high voltage GaN-on-diamond power devices

Fabrication of high performance AlGaN/GaN FinFET by utilizing anisotropic wet etching in TMAH solution

EDMOS in ultrathin FDSOI: Effect of doping and layout of the drift region

Monolithically integrated optical random pulse generator in high voltage CMOS technology

Energy harvesting with on-chip solar cells and integrated DC/DC converter

Compact heterodyne NEMS oscillator for sensing applications

Piezoresistive transduction optimization of p-doped poly-Silicon NEMS

Fast high power capacitive RF-MEMS switch for X-Band applications

Charge transfer speed analysis in pinned photodiode CMOS image sensors based on a pulsed storage-gate method

Scalability of planar FDSOI and FinFETs and What's in store for the future beyond that?

UTBB FDSOI technology flexibility for ultra low power internet-of-things applications

(Invited) silicene and phosphorene: Progress on the intriguing case of buckled atomic sheets

Interplay between hot carrier and bias stress components in single-layer double-gated graphene field-effect transistors

Characterization and modeling of low-frequency noise in CVD-grown graphene FETs

A new physics-based compact model for Bilayer Graphene Field-Effect Transistors

Systematic comparison of metal contacts on CVD graphene

Sensors and the internet of things

A multi-functional 200,000 lines/s tri-linear RGB line-scan sensor

Unified system level model of adsorption/desorption process and sensing electronics for vapor trace detection of different molecules in the air

Concept for a security aware automatic fare collection system using HF/UHF dual band RFID transponders

Step tunneling-enhanced hot-electron injection in vertical graphene base transistors

Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array

Physical and electrical characterization of Mg-doped ZnO thin-film transistors

Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model

Metal gate V modulation using PLAD N implants for Ge p-FinFET applications

The defect-centric perspective of device and circuit reliability — From individual defects to circuits

Experimental evidences and simulations of trap generation along a percolation path

Threshold voltage and on-current Variability related to interface traps spatial distribution

Reliability aspects of TiSi-Schottky barrier diodes in a SiGe BiCMOS technology

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow

Optimization of Trigate-On-Insulator MOSFET aspect ratio with MASTAR

Effective work function engineering by sacrificial lanthanum diffusion on HfON-based 14 nm NFET devices

Sharp-switching $Z^{2}-FET$ device in 14 nm FDSOI technology

Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process

New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering

Engineering of a TiN\Al\(Hf, Al)O\Hf RRAM cell for fast operation at low current

Benefit of Al bilayer for BEOL RRAM integration through 16kb memory cut characterization

Characterization of anomalous Random Telegraph Noise in Resistive Random Access Memory

Improving the resistive switching uniformity of forming-free TiO based devices by embedded Pt nanocrystals

Back-gate effects and detailed characterization of junctionless transistor

Low-frequency noise in bare SOI wafers: Experiments and model

Thin-film SOI PIN-diode leakage current dependence on back-gate-potential and HCI traps

H annealing for metallic contaminant reduction in BCD-SOI process: Benefits and drawbacks

Contact resistance extraction methods for CNTFETs

Analysis of InAs-Si heterojunction double-gate tunnel FETs with vertical tunneling paths

Improved surface roughness modeling and mobility projections in thin film MOSFETs

Predictive physical simulation of III/V quantum-well MISFETs for logic applications

Strain engineering of single-layer MoS

Electric performance of AlGaN/GaN heterojunction devices: A full-quantum study

2014 44th European Solid State Device Research Conference (ESSDERC)

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2010 Proceedings of the European Solid State Device Research Conference

2009 Proceedings of the European Solid State Device Research Conference

ESSDERC 2008 - 38th European Solid-State Device Research Conference

ESSDERC 2007 - 37th European Solid State Device Research Conference

2006 European Solid-State Device Research Conference

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.

32nd European Solid-State Device Research Conference

31st European Solid-State Device Research Conference

30th European Solid-State Device Research Conference

29th European Solid-State Device Research Conference

28th European Solid-State Device Research Conference

27th European Solid-State Device Research Conference

ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference

ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference

ESSDERC '94: 24th European Solid State Device Research Conference

ESSDERC '93: 23rd European solid State Device Research Conference

ESSDERC '92: 22nd European Solid State Device Research conference

ESSDERC '91: 21st European Solid State Device Research Conference

ESSDERC '90: 20th European Solid State Device Research Conference

ESSDERC '89: 19th European Solid State Device Research Conference

ESSDERC '88: 18th European Solid State Device Research Conference

ESSDERC '87: 17th European Solid State Device Research Conference

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in