NDLI: Charge transfer speed analysis in pinned photodiode CMOS image sensors based on a pulsed storage-gate method

Content Provider	IEEE Xplore Digital Library
Author	Pelamatti, A. Goiffon, V. Chabane, A. Magnan, P. Virmontois, C. Saint-Pe, O. de Boisanger, M.B.
Copyright Year	2015
Description	Author affiliation: Airbus Defence & Space, Toulouse, France (Saint-Pe, O.; de Boisanger, M.B.) \|\| Inst. Super. de l'Aeronautique et de l'Espace, Univ. de Toulouse, Toulouse, France (Pelamatti, A.; Goiffon, V.; Chabane, A.; Magnan, P.) \|\| Centre Nat. d'Etudes Spatiales, Toulouse, France (Virmontois, C.)
Abstract	Driven by low noise applications, Pinned Photodiode (PPD) [1]-[3] CMOS Image Sensors (CIS) have recently become the main image sensors technology for both commercial and scientific applications. The PPD (schematized in Fig. 1a) consists in a buried photodiode, where the surface p+ implant, also referred to as pinning-implant, pins the surface at the substrate potential. This peculiar structure not only reduces the dark current (by isolating the PPD from the charges generated at the $SiO_{2}-Si$ interface), but also limits the maximum PPD potential, often referred to as pinning voltage [4], which corresponds to the full depletion condition. The presence of this “potential floor” enables true charge transfer from the PPD to the collection node (or to another buried channel), whereas in standard photodiodes only charge sharing between two capacitances is possible. The combination of these unique features has led in the last decade to the development of several PPD-based detectors for high speed applications, such as Time of Flight (ToF) applications [5]-[8], which require high speed readout of small packets of photo-charges. One of the main challenges involved in PPD-based high speed detectors is to reach the best temporal resolution by maximizing the charge transfer speed from the photo-generation site to the collection node. The transfer speed becomes even more critical for applications, such as space imaging applications, which require pixel pitches of several tens of μm (for example for optics-related constraints [9]). In the last decade much effort has been put into improving charge transfer speed by introducing a drift field in the PPD by modulating the PPD local potential [5], [7], [10]-[13]. However the existing solutions often involve design and/or geometrical constraints, can require the use of a custom technology, or might not be implementable for large pixel pitches (where only a small drift field can be induced, as the maximum potential variation which can be generated within the PPD is equal to the pinning voltage [14], which is often of the order of 1V, or lower, to ensure optimum charge transfer toward the floating diffusion (FD)).
Starting Page	156
Ending Page	159
File Size	326991
Page Count	4
File Format	PDF
ISBN	9781467371339
ISSN	19308876
e-ISBN	9781467371353
DOI	10.1109/ESSDERC.2015.7324737
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-14
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Charge transfer Photodiodes Electric potential Logic gates CMOS image sensors
Content Type	Text
Resource Type	Article

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