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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kaczer, B. Franco, J. Weckx, P. Roussel, P.J. Bury, E. Cho, M. Degraeve, R. Linten, D. Groeseneken, G. Kukner, H. Raghavan, P. Catthoor, F. Rzepa, G. Goes, W. Grasser, T. |
| Copyright Year | 2015 |
| Description | Author affiliation: imec, Leuven, Belgium (Kaczer, B.; Franco, J.; Weckx, P.; Roussel, P.J.; Bury, E.; Cho, M.; Degraeve, R.; Linten, D.; Groeseneken, G.; Kukner, H.; Raghavan, P.; Catthoor, F.) || TUWien, Vienna, Austria (Rzepa, G.; Goes, W.; Grasser, T.) |
| Abstract | As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability variability) is an emerging trend that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects and their time, voltage, and temperature dependent properties. The properties of gate oxide defects are discussed and it is shown how these properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits. |
| Starting Page | 218 |
| Ending Page | 225 |
| File Size | 1366161 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781467371339 |
| ISSN | 19308876 |
| e-ISBN | 9781467371353 |
| DOI | 10.1109/ESSDERC.2015.7324754 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-09-14 |
| Publisher Place | Austria |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Stress Degradation Integrated circuit reliability Field effect transistors Integrated circuit modeling circuit simulations variability reliability defects RTN BTI HCI |
| Content Type | Text |
| Resource Type | Article |
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