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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jian-Shiun Chen Chingwei Yeh Jinn-Shyan Wang |
| Copyright Year | 2013 |
| Description | Author affiliation: Nat. Chung Cheng Univ., Chaiyi, Taiwan (Jian-Shiun Chen; Chingwei Yeh; Jinn-Shyan Wang) |
| Abstract | Using ultra low-voltage (ULV) is a viable approach towards lowering power consumption. However, due to the narrowing gap between the supply voltage and the threshold voltage, ULV designs inevitably suffer from either low performance or high leakage [1, 2]. Specifically, for applications that demand performance, low-threshold devices must be used and so leakage remains a significant problem. The most effective approach to cutting down leakage is power gating. In this regard, the SCCMOS [3] (Fig. 24.4.1, left) uses additional boost signals to “super cutoff” the leakage current. In SCCMOS, a charge pump is used to generate the boost signal, and the pump has to be on during the standby period to maintain the boost signal. As such, the leakage saved by the super cutoff may be far less than that consumed by the charge pump, negating the power advantages of ULV SCCMOS. |
| Sponsorship | IEEE Solid-State Circuits Soc. |
| Starting Page | 426 |
| Ending Page | 427 |
| File Size | 245044 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781467345156 |
| ISSN | 01936530 |
| e-ISBN | 9781467345163 |
| DOI | 10.1109/ISSCC.2013.6487799 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-02-17 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Switches Clocks Reduced instruction set computing Solid state circuits CMOS integrated circuits Leakage currents |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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