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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Warnock, J. Chan, Y.H. Harrer, H. Rude, D. Puri, R. Carey, S. Salem, G. Mayer, G. Yiu-Hing Chan Mayo, M. Jatkowski, A. Strevig, G. Sigal, L. Datta, A. Gattiker, A. Bansal, A. Malone, D. Strach, T. Huajun Wen Pak-Kin Mak Chung-Lung Shum Plass, D. Webb, C. |
| Copyright Year | 2013 |
| Description | Author affiliation: IBM Syst. & Technol. Group, Poughkeepsie, NY, USA (Chan, Y.H.; Rude, D.; Carey, S.; Yiu-Hing Chan; Mayo, M.; Jatkowski, A.; Malone, D.; Pak-Kin Mak; Chung-Lung Shum; Plass, D.; Webb, C.) || IBM Syst. & Technol. Group, Austin, TX, USA (Strevig, G.; Huajun Wen) || IBM Syst. & Technol. Group, Boeblingen, Germany (Harrer, H.; Mayer, G.; Gattiker, A.; Strach, T.) || IBM Syst. & Technol. Group, Williston, VT, USA (Salem, G.) || IBM Syst. & Technol. Group, Bangalore, India (Datta, A.) || IBM Res., Yorktown Heights, NY, USA (Puri, R.; Sigal, L.; Bansal, A.) || IBM Syst. & Technol. Group, Yorktown Heights, NY, USA (Warnock, J.) |
| Abstract | The new System z microprocessor chip (“CP chip”) features a high-frequency processor core running at 5.5GHz in a 32nm high-κ CMOS technology [1], using 15 levels of metal. This chip is a successor to the 45nm product [2], with significant improvements made to the core and nest (i.e. the logic external to the cores) in order to increase the performance and throughput of the design. Also, special considerations were necessary to ensure robust circuit operation in the high-κ technology used for implementation. As seen in the die photo, the chip contains 6 processor cores (compared to 4 cores in the 45nm version), and a large shared 48MB DRAM L3 cache. Each core includes a pair of data and instruction L2 SRAM caches of 1MB each. In addition, the chip contains a memory control unit (MCU), an I/O bus controller (GX), and two sets of interfaces to the L4 cache chips (also in 32nm technology). The CP chip occupies 598 $mm^{2},$ contains about 2.75B transistors, and has 1071 signal IOs. |
| Sponsorship | IEEE Solid-State Circuits Soc. |
| Starting Page | 46 |
| Ending Page | 47 |
| File Size | 268003 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781467345156 |
| ISSN | 01936530 |
| e-ISBN | 9781467345163 |
| DOI | 10.1109/ISSCC.2013.6487630 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-02-17 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Program processors Logic gates Reliability Synchronization Stress CMOS integrated circuits Routing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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