NDLI: A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS

Content Provider	IEEE Xplore Digital Library
Author	Kwangmo Jung Amirkhany, A. Kaviani, K.
Copyright Year	2013
Description	Author affiliation: Rambus, Sunnyvale, CA, USA (Amirkhany, A.; Kaviani, K.) \|\| Univ. of California, Berkeley, Berkeley, CA, USA (Kwangmo Jung)
Abstract	A decision-feedback equalizer (DFE) reconstructs the post-cursor inter-symbol interference (ISI) pattern from the detected data sequence and subtracts it from the received signal before detecting the next symbol. Therefore, DFE's operating speed is fundamentally limited by a 1-unit-interval (UI) feedback loop that is often the critical path in high-speed designs. Partial-response DFE (prDFE) architectures push the feedback loop away from the analog front-end to the post-slicer domain by making redundant decisions, as shown in Fig. 2.8.1(a). Since distinction between post and current data requires a sequential element to prevent a race, a latch overhead exists in the critical path of many prDFE designs [1]. For a 1-tap prDFE, the design in [2] entirely eliminates the sequential element from the critical path leveraging a unique race-free property of 1-tap half-rate prDFE. However, the architecture is not extendable to larger number of taps. For a 2-tap prDFE, overhead of the sequential element is reduced in a quarter-rate architecture. Figure 2.8.1(b) shows the block diagram of a receiver front-end with a shared CTLE, half-rate slicers and a quarter-rate prDFE. The critical path in the quarter-rate implementation is limited by a 2:1 mux delay $(T_{mux})$ and a flop setup and clock-to-output overhead $(T_{FF}),$ as shown in Fig. 2.8.2(a). Assuming $T_{FF}$ = $2T_{mux},$ the loop delay increases by 200% compared to the absolute minimum for speculation, $T_{mux}.$ Figure 2.8.2(a) also shows the race that is prevented by employing the sequential elements in a quarter-rate implementation.
Sponsorship	IEEE Solid-State Circuits Soc.
Starting Page	42
Ending Page	43
File Size	1073412
Page Count	2
File Format	PDF
ISBN	9781467345156
ISSN	01936530
e-ISBN	9781467345163
DOI	10.1109/ISSCC.2013.6487629
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Receivers Decision feedback equalizers Clocks Delays Latches Prototypes
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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