NDLI: An 18 ns 56-bit multiply-adder circuit

Content Provider	IEEE Xplore Digital Library
Author	Montoye, R.K. Cook, P.W. Hokenek, E. Havreluk, R.P.
Copyright Year	1990
Description	Author affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Montoye, R.K.; Cook, P.W.; Hokenek, E.; Havreluk, R.P.)
Abstract	A multiply-adder that achieves a 56-b X*X+Z function with cycle time of 18 ns in a 1- mu m CMOS technology is discussed. The organization requires only two pipeline stages, ensuring quick recovery from branch instructions. The design is for the fraction part of a 64-b multiply-adder and is itself 56 b wide at input and output. To achieve high performance and reasonable density, it uses Booth encoding and a Wallace tree array. Data are captured at the input latches and routed immediately to the Booth encoders, which, in addition to encoding the X input, also provide driven Y and Y-bar signals for the array. The Z input is also captured and routed to the Z shifter. Encoded X, Y-bar, and Z and shifted Z signals are all routed to the partial product array. Booth encoding for 56 b produces 29 partial products; the Z input raises the number of terms to be added to 30. The partial product array reduces this to three, at which point a second latch captures the reduced result. After the latch, the three terms are reduced to two in a full adder, and the resulting two terms added and renormalized.
Starting Page	46
Ending Page	47
File Size	376790
Page Count	2
File Format	PDF
DOI	10.1109/ISSCC.1990.110122
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-02-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Pipelines Latches Compressors CMOS technology Encoding Adders Wiring Decoding Very large scale integration
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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