NDLI: An 18 b 10 mu s self-calibrating ADC

Content Provider	IEEE Xplore Digital Library
Author	Miller, G. Timko, M. Lee, H.-S. Nestler, E. Mueck, M. Ferguson, P.
Copyright Year	1990
Description	Author affiliation: Analog Devices Semicond., Wilmington, MA, USA (Miller, G.; Timko, M.; Lee, H.-S.; Nestler, E.; Mueck, M.; Ferguson, P.)
Abstract	A self-calibrating, 18-b, serial-output, 100-ksample/s analog-to-digital converter (ADC) which is implemented on a 24-V BiCMOS analog chip and a 5-V, 2- mu m CMOS digital chip is described. This partitioning allows a larger input signal for better dynamic range, eases the comparator design, and protects analog circuitry from digital feedthrough. The two chips are wired in a 7.6-mm-wide, 16-pin plastic dual inline package (DIP). Thirteen inter-chip bonds make up the control and data interface. The only other common connections to the logic supply and its ground return are made through separate wires for each chip. The analog chip is a charge-balancing converter consisting of an 18-b calibrated digital-to-analog converter (DAC), an auto-zeroed latching comparator, buffers for all analog inputs, and logic for the self-timed interface to the digital chip. The digital chip is a custom microcontroller which implements the calibration aid conversion algorithms, as well as the digital part of the user interface. The data path on this chip includes calibration pattern generators, a successive approximation register (SAR), elements for calculating the error terms, and RAM for storing those terms.
Sponsorship	IEEE Bar Area Council Univ. Pennsylvania
Starting Page	168
Ending Page	169
File Size	858952
Page Count	2
File Format	PDF
DOI	10.1109/ISSCC.1990.110180
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-02-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analog-digital conversion Logic Calibration BiCMOS integrated circuits Dynamic range Signal design Protection Plastic packaging Electronics packaging Wires
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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