NDLI: A 5 ns 369 kb port-configurable embedded SRAM with 0.5 mu m CMOS gate array

Content Provider	IEEE Xplore Digital Library
Author	Sawada, K. Takayanagi, T. Nogami, K. Takahashi, M. Uchida, M. Itoh, Y. Kobayashi, S. Noda, M. Matsuoka, F. Oyamatsu, H. Kakumu, M. Maeguchi, K. Iizuka, T.
Copyright Year	1990
Description	Author affiliation: Toshiba Corp., Kawasaki, Japan (Sawada, K.; Takayanagi, T.; Nogami, K.; Takahashi, M.; Uchida, M.; Itoh, Y.; Kobayashi, S.; Noda, M.; Matsuoka, F.; Oyamatsu, H.; Kakumu, M.; Maeguchi, K.; Iizuka, T.)
Abstract	An SRAM that has column-sliceable peripheral circuitry embedded in a 235 K CMOS gate array and improved flexibility in configuration is described. The port-configurable (PC) SRAM cell achieves the minimum area overhead associated with the configurability by using four port-customization terminals at every memory-cell boundary. Prior to customization, first and second polysilicon are used to connect the internal memory-cell nodes to the port-customization terminals. Multiport SRAMs are configured by first Al so that corresponding internal nodes of adjacent memory cells are connected. At the same time, word lines are configured according to the port customization using second Al and the via hole. The use of second Al is a key to the density and speed. A high-resistance polysilicon load cell is used to provide good write operation and high density. The cell size is 9*13.6 mu m, one-tenth the area of an equivalent multiport cell based on gate-array basic cells. The worst-case access speed of multiport configuration based on this scheme has no dependence on the number of ports because the memory-cell current available to drive unit bit-line load capacitance remains constant. In the multiport configuration, the write operation from one port must flip all of the connecting cells through the NMOS transfer gate of the write port cell. Therefore, a six-transistor full CMOS SRAM cell is not suitable for PC SRAM.
Sponsorship	IEEE Bar Area Council Univ. Pennsylvania
Starting Page	226
Ending Page	227
File Size	261957
Page Count	2
File Format	PDF
DOI	10.1109/ISSCC.1990.110207
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-02-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Artificial intelligence MOS devices Decoding Operational amplifiers Differential amplifiers MOSFETs Semiconductor devices CMOS memory circuits Capacitance
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 12ns 256k Bicmos Sram

A 15-ns 1-Mbit CMOS SRAM

A 9 ns 1 Mb CMOS SRAM

A 0.8 mu m 29000 gate BICMOS-ECL mixed array with 40 kb/5 ns embedded SRAM

A programmable floating-gate voltage reference in 0.5 /spl mu/m CMOS

0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache

A 23 ns 4 Mb CMOS SRAM with 0.5 mu A standby current

A 20 ns 4 Mb CMOS SRAM with hierarchical word decoding architecture

A 1.3 mu m BiCMOS gate array with configurable on-chip 3-port RAM

A 5 ns 369 kb port-configurable embedded SRAM with 0.5 mu m CMOS gate array

Similar Documents

A 12ns 256k Bicmos Sram

A 15-ns 1-Mbit CMOS SRAM

A 9 ns 1 Mb CMOS SRAM

A 0.8 mu m 29000 gate BICMOS-ECL mixed array with 40 kb/5 ns embedded SRAM

A programmable floating-gate voltage reference in 0.5 /spl mu/m CMOS

0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache

A 23 ns 4 Mb CMOS SRAM with 0.5 mu A standby current

A 20 ns 4 Mb CMOS SRAM with hierarchical word decoding architecture

A 1.3 mu m BiCMOS gate array with configurable on-chip 3-port RAM

A 5 ns 369 kb port-configurable embedded SRAM with 0.5 mu m CMOS gate array