NDLI: Advanced silicide for sub-0.18 /spl mu/m CMOS on ultra-thin (35 /spl mu/m) SOI

Content Provider	IEEE Xplore Digital Library
Author	Ren, L.P. Baohong Cheng Woo, J.C.S.
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA (Ren, L.P.)
Abstract	As CMOS device dimensions are scaled toward 0.1 /spl mu/m, formation of controllable thin silicide is critical. For conventional high temperature Ti salicidation, however, it is difficult to control silicide formation due to a fast reaction rate between Ti metal and silicon. Co silicide can achieve low sheet resistance for fine polysilicon lines and source/drain (S/D) regions, but the diode leakage is still a major problem with shallower junctions and SOI for deep sub-micron CMOS (Hsiao et al., 1998). In the past, a low temperature silicide technology has been proposed and applied to 100-nm SOI MOSFETs (Goto et al., 1995). In this paper, Ge/sup +/ pre-amorphized Ti salicide for sub-0.1 /spl mu/m gate length CMOS is investigated in detail and is used to demonstrate 0.1 /spl mu/m CMOS on an ultra thin SOI film of 35 nm for the first time. We focused on the influence of Ge/sup +/ pre-amorphization energy, Ti metal thickness and substrate doping on Ti silicidation kinetics, silicide depth and sheet resistance on bulk and fine polysilicon lines ranging from 1.0 to 0.1 /spl mu/m. Our results showed an effective control of silicide depth in the case of Ge/sup +/-implanted samples. A small grain size averaging 80 nm was observed on fine gate lines and polysilicon lines down to 0.1 m were shown to have good resistivity. The effects of metal thickness and doping species were eliminated. The excellent device performance shows this technology is highly suitable for future 0.1 /spl mu/m SOI MOSFETs and deep sub-micron bulk CMOS devices.
Sponsorship	IEEE Electron Devices Soc
Starting Page	88
Ending Page	89
File Size	151343
Page Count	2
File Format	PDF
ISBN	0780354567
ISSN	1078621X
DOI	10.1109/SOI.1999.819866
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicides CMOS technology MOSFETs Doping Temperature control Silicon Diodes Substrates Silicidation Kinetic theory
Content Type	Text
Resource Type	Article

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