NDLI: Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits

Content Provider	IEEE Xplore Digital Library
Author	Aller, I. Kroell, K.E.
Copyright Year	1999
Description	Author affiliation: IBM Entwicklung GmbH, Boeblingen, Germany (Aller, I.)
Abstract	Circuit design using partially depleted (PD) SOI FETs must take into account a variable gate delay which is dependent on the switching history of the circuits (Gautier et al, 1997; Houston and Unnikrishnan, 1998). In order to fully exploit the advantages of SOI, it is important to understand and analyze such 'history effects' and consider them for an optimized design strategy. In this paper, we describe a methodology suitable to analyze PD SOI CMOS circuits, including a new algorithm for dynamic equilibrium computations, a task that is not practicable with standard circuit simulators because of the very slow evolution of the body potential (time constants up to ms (Assaderaghi et al., 1996)). Simulation results for a 0.2 /spl mu/m technology are given, showing the importance of design and application parameters with regard to the history effect.
Sponsorship	IEEE Electron Devices Soc
Starting Page	40
Ending Page	41
File Size	144724
Page Count	2
File Format	PDF
ISBN	0780354567
ISSN	1078621X
DOI	10.1109/SOI.1999.819848
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay History Computational modeling Circuit simulation Circuit synthesis FETs Switching circuits Design optimization Algorithm design and analysis Heuristic algorithms
Content Type	Text
Resource Type	Article

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