NDLI: "Gated-diode" in SOI MOSFETs: a sensitive tool for characterizing the buried Si-SiO/sub 2/ interface

Content Provider	IEEE Xplore Digital Library
Author	Xuejun Zhao Ioannou, D.E.
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA (Xuejun Zhao)
Abstract	Summary form only given. A critical factor in the development of SOI wafers and related CMOS technologies is the quality of the buried Si-SiO/sub 2/ interface. Careful wafer preparation is necessary to obtain reduced surface state density in order to suppress back channel leakage and improve hot carrier reliability and radiation hardness. However, the measurement of the back interface properties and in particular the interface state density remains one of the most difficult parameters to measure in SOI transistors. This is because the large thickness of the buried oxide (relative to gate oxide) renders the usual techniques insensitive and very difficult to apply (Ioannou et al., 1991; Wuters et al., 1989). There has recently been renewed interest in an old technique based on the gated-diode concept (Grove and Fitzelard, 1966), new refinements and modifications of which are being used for the study of current bulk CMOS technologies (Cai and Sah, 1999; Guan et al., 1999). The purpose of this paper is to explain how the presence of two channels makes the adaptation of this technique particularly useful for SOI MOSFETs and suitable for evaluation of the buried interface. The present approach is distinct from and complementary to a recently published modification of the gated-diode technique applied to dual-gate SOI devices for measurement of the recombination lifetime (Ernst et al., 1999).
Sponsorship	IEEE Electron Devices Soc
Starting Page	52
Ending Page	53
File Size	149032
Page Count	2
File Format	PDF
ISBN	0780354567
ISSN	1078621X
DOI	10.1109/SOI.1999.819854
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Diodes MOS devices Voltage Stress Density measurement Artificial intelligence
Content Type	Text
Resource Type	Article

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Gated-diode in SOI MOSFETs: a sensitive tool for characterizing the buried Si/SiO/sub 2/ interface

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