NDLI: A dynamic body discharge technique for SOI circuit applications

Content Provider	IEEE Xplore Digital Library
Author	Kuang, J.B. Saccamango, M.J. Lu, P.F. Chuang, C.T. Assaderaghi, F.
Copyright Year	1999
Description	Author affiliation: IBM Corp., Rochester, MN, USA (Kuang, J.B.)
Abstract	It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-V/sub t/ floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.
Sponsorship	IEEE Electron Devices Soc
Starting Page	77
Ending Page	78
File Size	136417
Page Count	2
File Format	PDF
ISBN	0780354567
ISSN	1078621X
DOI	10.1109/SOI.1999.819861
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS logic circuits History Switches Operational amplifiers Timing Degradation CMOS analog integrated circuits Circuit topology Voltage Switching circuits
Content Type	Text
Resource Type	Article

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