NDLI: An abnormal floating gate interference and a low program performance in 2y nm NAND flash devices

Content Provider	IEEE Xplore Digital Library
Author	Eunmee Kwon Dongyean Oh Bonghoon Lee Jeong-hyong Yi Sangyong Kim Gyuseog Cho Sungkye Park Jaehoon Choi
Copyright Year	2011
Description	Author affiliation: R&D Division, Hynix Semiconductor Inc., San 136-1 Ami, Bubal, Icheon, Gyeonggi, 467-701, Korea (Eunmee Kwon; Dongyean Oh; Bonghoon Lee; Jeong-hyong Yi; Sangyong Kim; Gyuseog Cho; Sungkye Park; Jaehoon Choi)
Abstract	We have investigated a mechanism for an abnormally large floating gate (FG) interference reported in 2y nm NAND flash device. Based on the experimental and simulation results, we have found that the root cause is attributed to a depletion of polysilicon (poly-Si) layer for the control gate (CG). It was also found that the poly-Si depletion gives deterioration in the program performance. This work suggests that the poly-Si depletion of the CG should be controlled and considered utilizing a full 3-dimensional (3D) TCAD process and device simulations to improve the FG interference and the performance of NAND flash device beyond 2y nm technology.
Starting Page	207
Ending Page	210
File Size	1216483
Page Count	4
File Format	PDF
ISBN	9781612844190
ISSN	19461569
e-ISBN	9781612844183
DOI	10.1109/SISPAD.2011.6035087
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-08
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Interference Couplings Flash memory Capacitance Three dimensional displays Logic gates Electric potential 3D TCAD simulation Poly depletion NAND flash
Content Type	Text
Resource Type	Article

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